Recent years, phase-shifting masks have been often used for processing LSI (Large Scale Integrated) circuits in a nano-scale or a micro-scale, with advance of miniaturization, lower voltage and larger scale of the LSI circuits.
In logic LSI circuits or system LSI circuits, a mixed pattern is employed for a gate pattern, for example, which includes dense pitches and sparse pitches. Multiphase exposure methods utilizing a plurality of photo-masks are used for exposing such a mixed pattern with dense pitches and sparse pitches.
A multiphase exposure method is disclosed in Japanese Patent Application Publication (Kokai) No. 2003-149787. In the method, an exposure pattern is created on a resist layer by use of a Levenson type phase-shifting mask. After the exposure using the Levenson type phase-shifting mask, an exposure is carried out to remove unnecessary portions from the resist layer by use of a trimming mask which is a regular mask but not a phase-shifting mask. After the exposure using the trimming mask, a development process is carried out so that micro-scale resist patterns are formed.
The logic LSI circuits and system LSI circuits mentioned above need to be designed in consideration of driving capability, power consumption or leakage current of the transistors constituting the logic LSI circuits and system LSI circuits. In order to meet such a requirement, micro-scale patterns which are different from one another in dimensional width need to be formed depending on the characteristics of the transistor.
In the photo-mask disclosed in the patent publication, non-phase shifter parts, narrow and elongated light shielding patterns and phase shifter parts are formed in an alternating series arrangement. However, the patent publication does not describe any configuration to prevent increase in area of layouts of the LSI circuits, in a case where micro-scale patterns with different dimensional width are created in the same phase-shifting mask.